This invention relates primarily to dielectricaly isolated devices within semiconductor integrated circuits, and particularly, to such devices having "vertical" configurations providing high voltage capability. The invention also relates to discrete DMOS devices, particularly to Double Diffusion Metal Oxide Semiconductor (DMOS) and Insulated Gate Bipolar Transistor (IGBT) devices.
Integrated circuits with which the present invention has utility are known. One class of such circuits is described in "An Analog/Digital BCDMOS Technology with Dielectric Isolation-Devices and Processes", Chih-Yuan Lu, et al, IEEE Transactions on Electron Devices, Vol. 35, No. 2, February 1988, pages 230-237. In such integrated circuits, various different types of semiconductor devices, e.g., bipolar, Complimentary MOS (CMOS), DMOS, p-n-p-n, Junction FET (JFET) and Dual Gate DMOS (DGDMOS) devices are integrated within a single semiconductor chip. This is made possible by the use of device structures and processes which are compatible with all the different types of devices included on the chip, even though not all the devices are optimized in their performance. In particular, and with respect to the present invention, in order to provide certain ones of the devices with high voltage capability, particularly the DMOS and IGBT devices (described further hereinafter), the devices are formed within deep tubs providing large vertical distances for withstanding high voltages. Doped regions are formed at both the top and bottom surfaces of the tubs, and, in the different devices within the chip, the different doped regions provide different functions, depending upon the particular devices involved. For example, in the DMOS devices, the bottom doped region serves as a highly conductive channel for current passing between source and drain regions of the device. In bipolar transistors, the bottom doped region serves as the device collector. A problem, however, is that while the distance of the bottom doped regions from the upper doped regions is optimized for the DMOS devices, such distance is generally higher than optimal for the other devices within the chip.
The present invention has utility for better optimizing the dimensions of various devices in integrated circuits of the type described above.
In addition, the present invention has utility in DMOS and IGBT devices in general, whether integrated or not.
DMOS devices are well known, wherein the "D" stands for "diffusion" or "double diffusion". Such devices comprise (FIG. 1) a substrate 10 of semiconductor material having on a surface thereof a layer 12 of gate oxide covered by a gate electrode 14. The device is of cellular type, including spaced apart portions connected in parallel. Plural source regions comprise first doped regions 16, e.g. of N type conductivity, formed within second doped regions 18 of opposite type conductivity, e.g. of P type conductivity, with the regions 18 being formed within the substrate, e.g. of N type conductivity. The regions 16 and 18 are formed by successive ion implantations using the gate electrode 14 as a mask and by heating for causing lateral diffusions of the various regions under the gate electrode. The second doped regions 18 extend laterally further beneath the gate oxide than the first regions 16, and the portions 20 of the second regions 18 extending beyond the first regions 16 beneath the gate oxide comprise the channel regions of the device. The gate electrode 14 also overlies surface portions 22 of the N type substrate 10. The substrate beneath the surface portions 22 comprises the drain region of the device.
In operation, when the channel regions 20 are in a conductive state, under control of the gate electrode, current flows from a source electrode 24 contacting surface portions of the first 16 and second 18 regions through the first regions 16, through the channel regions 20, and into the substrate 10 at the surface portions 22. The current flows through the substrate 10 (drain region) to a drain electrode 26 contacting the substrate surface at a position laterally remote from the first and second regions.
Such DMOS devices are used in power controlling applications involving relatively high voltages and currents and, to this end, the substrate portions directly adjoining the second regions 18 are lightly doped and overlie a heavily doped region 28 which extends laterally along the bottom of the substrate and then vertically upwardly to the drain electrode 26. Accordingly, when the device is in the switched-on state, current flows first laterally through the channel regions 20 beneath the gate electrode 12 to the substrate portions 22 and then vertically downwardly through the substrate 10 to the underlying heavily doped region 28 which conducts the current to the drain electrode 26.
When the device is in its switched-off state, with a voltage applied between the source and drain regions, the applied voltage is "withstood" across the p-n junctions 30 between the P regions 18 and the N substrate 10; that is, the applied voltage reverse biases the p-n junctions 30. Depletion regions are thus formed on opposite sides of the p-n junctions 30, and, because of the low doping of the substrate (much lower than that of the second region 18) the width of the depletion regions within the substrate 10 primarily determines the stand-off voltage capability of the device. The maximum widths of the depletion regions correspond substantially to the distance between the p-n junctions 30 and the heavily doped region 28 beneath the second regions 18. Thus, when the depletion regions reach the heavily doped region 28, further expansion of the depletion regions with increasing applied voltage substantially ceases, the electric field intensity through the substrate increases, and voltage breakdown of the device occurs.
The vertical distance Ba between the second regions 18 and the underlying region 28 largely influences two parameters of the device. One parameter is the on-current resistance of the device because the current flows through this vertical distance to reach the region 28. The other parameter is the breakdown voltage rating of the device. The vertical distance, however, has opposite effects on these two parameters. A desired low on-current resistance requires a short vertical distance, while a desired high voltage breakdown requires a long vertical length.
Insulated Gate Bipolar Transistors (IGBT) can be identical to the DMOS devices illustrated in FIG. 1 except that the high conductivity region 28 is of opposite type conductivity to that of the overlying region 10. In terms of the foregoing, conflicting requirements of DMOS devices are also present in IGBT devices.
The present invention provides a means for better reconciling these conflicting requirements. Also, as described hereinafter, such reconciling means is useful in integrated circuits of the type hereinafter described for better optimizing the characteristics of various types of devices contained therein.